I2C Bus Design Notes: Pull-Ups, Capacitance and Level Shifting

*This is an engineering design note, not a report of a completed installation. It describes how an I2C bus is dimensioned and where it usually goes wrong; the values are general design guidance and must be confirmed against the datasheet for the devices you select.*

Why I2C is harder than it looks. The bus is open-drain: every device can pull a line low, and nothing drives it high. The high level is produced by a resistor charging the total bus capacitance, which makes the rise time a function of the whole bus rather than of any one device. That is the entire difficulty of I2C design, and it is invisible on a schematic.

The parameter that decides everything: total bus capacitance. Add the pin capacitance of every device on the bus, the capacitance of the traces, and the capacitance of the connector if the bus leaves the board. The standard sets a maximum bus capacitance for each mode, and the rise-time requirement follows from it. Because the contributor that is easiest to forget is the connector and cable, buses that work on the bench and fail in the assembled product are usually buses that grew capacitance when they were cabled.

Sizing the pull-ups. The pull-up has two constraints pulling in opposite directions. It must be small enough that the total bus capacitance charges to the high-level threshold within the allowed rise time, and large enough that a device pulling the line low sinks an acceptable current at the low-level threshold. The minimum value comes from the sink current the weakest device can handle; the maximum value comes from the rise-time budget and the bus capacitance. The usable window between them narrows as the bus capacitance grows, and if the window closes, the answer is not a compromise resistor but fewer devices, a shorter bus, or an active buffer.

Multiple voltage domains. When devices on the same bus run from different supplies, the pull-up can only go to one of them, and the other domain sees a voltage above its own supply. A level shifter is then required, and the common realisation is a dedicated I2C translator built around a pass device with the pull-ups on both sides. Two cautions follow. A translator is not transparent: it adds capacitance and propagation delay to the budget. And the series resistors sometimes added “for protection” interact with the pull-ups and the translator’s own capacitance, so they are a deliberate design choice rather than a free addition.

Bus speed and clock stretching. The bus speed sets the rise-time budget directly, which is why a bus that is marginal at the standard rate can be made to work by dropping to the low-speed mode — a legitimate engineering answer, not a failure. Clock stretching, where a target holds the clock line low, extends the transaction and is a normal part of the protocol; the controller must support it, and a bus that fails intermittently under load is often a stretching timeout rather than a signal integrity problem.

Layout and topology. I2C is a bus, and buses are laid out as a chain rather than a star where the layout allows, to keep the stubs short. Long stubs add capacitance and create reflections that the open-drain driver cannot damp. Keep the pull-ups near the point where the bus capacitance is concentrated, and keep the two lines routed together so that noise couples into them as a common mode rather than differentially.

What to verify before committing. Total bus capacitance against the mode’s limit. The pull-up window from both directions: sink current of the weakest device and rise time at the total capacitance. Translator delay and capacitance in the budget if domains are mixed. And clock-stretching support in the controller for every target on the bus.

This design note describes general I2C bus practice. Confirm bus capacitance limits, timing requirements, sink currents and translator behaviour against the applicable specification and the datasheets for the exact devices you select.

Selecting devices for an I2C bus?

Send the part numbers and quantities through our RFQ form, or contact us and we will confirm availability and lead time. Our catalogue lists logic, interface and level-shifter parts by category.

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